1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of Related Art
In the data read operation of a semiconductor memory device such as a Dynamic Random Access Memory (DRAM), the data stored in a memory cell is first transferred to a sense amplifier from the memory cell via a column switch and is then amplified by the sense amplifier. The amplified data is transferred to the data output circuit and is then read out to an external circuit of the semiconductor memory device.
An enable signal is inputted to the data output circuit. If this signal is asserted, the data output circuit takes out the data from the sense amplifier and outputs the data as taken out to the external circuit.
Recently, a variety of researches and developments have been made with regard to the semiconductor memory device for the purposes of reducing the power consumption, increasing the withstand voltage of the gate oxide film in correspondence with the minuteness of the transistor, increasing the withstand voltage between the source and the drain of a transistor, and so forth. As one countermeasure to solve these problems, it has been proposed to use a voltage adjusted to be lower than the power source voltage of the external circuit (referred to as xe2x80x98external voltagexe2x80x99 hereinafter) Vext as the power source voltage of the internal circuit (referred to as xe2x80x98internal voltagexe2x80x99 hereinafter) Vint of the semiconductor memory device, and this proposal is already adopted widely by a variety of semiconductor memory devices.
In the semiconductor memory device of which the internal circuit is formed such that it operates with the internal voltage Vint, the maximum voltage of the data transmitted from the sense amplifier to the output circuit is the internal voltage Vint while the minimum voltage of it is the ground voltage GND. One hand, as the external circuit operates with the external voltage Vext, the conventional art data output circuit is provided with a voltage level shifter for shifting the voltage level of the data received from the sense amplifier from Vint/GND to Vext/GND.
However, in the conventional art semiconductor memory device of the class wherein the complementary data is given to the data output circuit from the sense amplifier, and the read data (output signal) to be outputted to the external circuit is generated from this complimentary data, it has been needed to prepare the level shifter for every complementary data. That is, every data output circuit has to have been provided with two level shifters so far.
The number of the data output circuits corresponds to the number of data bits as read out at a time, that is, the number of data output terminals. When comparing the DRAM of 8-bit I/O type with that of 16-bit I/O type, the number of data output circuits of the former is 8 while the number of data output circuits of the latter becomes 16. As each output circuit is provided with two level shifters, the number of the latter""s level shifters becomes larger than the former""s level shifters by 16.
As described above, in case of the conventional art semiconductor memory device, especially the one of the type having a lot of I/O terminals, the level shifter has used a considerably larger area in view of the whole layout area of circuit elements in the semiconductor memory device. Accordingly, the level shifters provided for the data output circuit have been one of factors hindering the reduction of the layout area of circuit elements forming the semiconductor memory device.
Furthermore, according to the conventional art semiconductor memory device as described above, the data transmitted from the sense amplifier to the data output circuit has been processed at the level shifter to convert the voltage level of the data and then outputted to the external circuit. In order to shorten the data read time, therefore, it is required to minimize or eliminate the time spent at the level shifter for converting the data voltage level.
The present invention has been made in view of the problems as described above, and the object thereof is to provide a semiconductor memory device which makes it possible to reduce the scale of the data output circuit, and to improve the data read speed.
In order to solve the problems as described above, according to the first aspect of the invention, there is provided a semiconductor memory device having an output portion (202) and an output control portion (201, 301).
The output portion applies the first power source voltage (Vext) to a read data output node (n232) when the first output control node (n/P) is in the active state, and applies the first power source reference voltage (GND) to the read data output node when the second output control node (n/N) is in the active state.
The output control portion receives the first output data determination signal (D) which makes the power source voltage transition to the second power source voltage (Vint) or the second power source reference voltage (GND) depending on the information stored in the selected memory cell; the second output data determination signal (/D) which makes the power source voltage transition to the second power source reference voltage when the first output data determination signal makes the power source voltage transition to the second power source voltage and makes the power source voltage transition to the second source voltage when the first output data determination signal makes power source transition to the second power source reference voltage; and an enable signal (EN_Vext) making the power source voltage transition to the first power source voltage or the first power source reference voltage. Furthermore, the output control portion makes the first output control node be in the active state when the enable signal makes the power source voltage transition to the first power source voltage and the first output data determination signal makes the power source voltage transition to the second power source voltage, and makes the second output control node be in the active state when the enable signal makes the power source voltage transition to the first power source voltage and the second output data determination signal makes the power source voltage transition to the second power source voltage. Still further, the output control portion includes the first latch means for latching the first output control node in the inactive state and the second latch means for latching the second output control node in the inactive state.
With this structure, it becomes possible to output, from the read data output node, an output signal (DOUT) swinging between the first power source voltage and the first power source reference voltage, based on the first output data determination signal and the second output data determination signal which swing between the second power source voltage and second power source reference voltage.
The output control portion is composed of the first transistor arranged for applying the first power source voltage to the first output control node; the second and third transistors arranged in series for applying the first power source reference voltage to the first output control node; the fourth transistor arranged for applying the first power source voltage to the second output control node; and the fifth and sixth transistors arranged in series for applying the first power source reference voltage to the second output control node. It is preferable that the first, second, fourth, and fifth transistors are on/off controlled by the enable signal, the third transistor is on/off controlled by the first output data determination signal, and the sixth transistor is on/off controlled by the second output data determination signal. With this, the circuit scale of the output control portion can be made smaller.
The first latch means detects that the second output control node is in the active state, and latches the first output control node in the inactive state, and the second latch means detects that the first output control node is in the active state, and latches the second output control node in the inactive state. With this structure, it is prevented that the first and second output control nodes stay in the active state at the same time.
Furthermore, according to the second aspect of the invention, there is provided another semiconductor memory device having an output portion (202) and output control portion (401, 501).
The output portion applies the first power source voltage (Vext) to a read data output node (n232) when the first output control node (n/P) is in the active state, and applies the first power source reference voltage (GND) to the read data output node when the second output control node (n/N) is in the active state.
The output control portion receives the first output data determination signal (D) which makes the power source voltage transition to the second power source voltage (Vint) or the second power source reference voltage (GND) depending on the information stored in the selected memory cell; the second output data determination signal (/D) which makes the power source voltage transition to the second power source reference voltage when the first output data determination signal makes the power source voltage transition to the second power source voltage and makes the power source voltage transition to the second source voltage when the first output data determination signal makes the power source voltage transition to the second power source reference voltage; and an enable signal (EN_Vext) making the power source voltage transition to the first power source voltage or the first power source reference voltage. And also, the output control portion makes the first output control node be in the active state when the enable signal makes the power source voltage transition to the first power source voltage and the first voltage difference is caused between the first output data determination signal and the second output data determination signal, and makes the second output control node be in the active state when the enable signal makes the power source voltage transition to the first power source voltage and the second voltage difference is caused between the first output data determination signal and the second output data determination signal. Furthermore, the output control portion includes the first latch means for latching the first output control node in the inactive state and the second latch means for latching the second output control node in the inactive state.
With this structure, it becomes possible to output with high speed, from the read data output node, an output signal (DOUT) swinging between the first power source voltage and the first power source reference voltage, based on the first output data determination signal and the second output data determination signal which swing between the second power source voltage and second power source reference voltage.
The first latch means detects that the enable signal makes the power source voltage transition to the first power source reference voltage, and latches the first output control node in the inactive state, and the second latch means detects that the enable signal makes the power source voltage transition to the first power source reference voltage, and latches the second output control node in the inactive state. With this structure, it is avoided that the first and second output control nodes stay in the electrically floating state, thereby erroneous operation due to the noise being prevented.
The output control portion detects the first voltage difference only when the second output control node is in the inactive state, and detects the second voltage difference only when the first output control node is in the inactive state. With this structure, it is prevented that the first and second output control nodes stay in the active state at the same time.
Certain preferred embodiments of the invention will now be described by way of examples and with reference to the accompanying drawings, wherein constituents of the invention having almost like function and structure in each of the several figures are identified by the like reference numeral or character, thereby omitting the redundant and repetitive description, and wherein: